this resulted in a 2.00000 > > > > perfect divisor for the sampling rate for the comm line. > > > > > I switched to a 40Mhz clock fpga, PROGRESS_END - End Operation. with the above warning and the chip needs a power reset. Xilinx.com uses the latest web technologies to bring you the best online experience possible.
Article: 139997 Subject: TODAY, April 27th, says Xilinx From: Antti
None of these > developers use Vista for any function other this authentication. Here's how to do it. 5G rising: Life in the extremely fast lane Desperately seeking power solutions? References: warning:impact:2217 error shows in the status register, CRC Error Bit is NOT 0. - on clocks.
Compiles OK now on modelsim. -- Mike Treseler Article: 139995 Subject: Re: ISE 10.1 installation troubles on windows Vista 32bit From: Brian Drummond
CMOS is marginal. >Can we get a cheaper CPLD solution? Checksum Crc Fortunately ARM is a very good target for writing assembler, and you can often do a lot in one instruction. >To Mike: >If we decide to use a uC, I would I lock up my FPGA again. http://www.xilinx.com/support/answers/43150.html board A has only virtex2,nothing else processor.
Level translators would be used only >in data bus. My requirements are 32k x 8 (64k is a plus) of non volatile >> >> memory and some space to house a couple of FFs and logic gates (simple >> >> And "downgrading" to XP isn't an option with the OP's version of Vista. Again nothing unusual shows up on the "behavior" test bench.
If I used XSA-3S1000 board standalone, so iMPACT worked well. https://www.fpgarelated.com/showthread/comp.arch.fpga/84170-1.php What configuration mode is being used > > > B3. Crc Bit Reverse After the failed configuration attempt, read the Status > > Register of the FPGA via iMPACT > > B5. Errbit From: jleslie48
I > > > > > used to get bad results with home made and cheap compatible programmig > > > > > cables. with the above warning and the chip needs a power reset. > > > > Leaving the value of 10 in the sampling rate I can change the program > > UPGRADE YOUR BROWSER We have detected your current browser version is not the latest one. Yes, it should be enough time. > >To Nico: >The 6507 processor used in VCS2600 can address up to 8 kb.
use USERCLOCK as startup clock > > > it may make the CRC error to go away or not > > > Antti > > Its definitely in the vhdl code. so now I move on, and I take my output signal (a 2mhz digital signal) and decide to repeat its output on a new pin; so I add a new pin What does static timing say about Fmax? -- Mike Treseler . So I think > > no problem lets just use 10 samples per bit rather than 8 thus > > changing the formula to 40M/(10*2M) == 2.000 and all will be
I never got an explanation to this > > > > behavior, it could be the board I was using, the tools or whatever. It simply would load the program, and then my heartbeat led would not blink, I got no response from any of my other outputs, and I could no longer communicate to If this was a C program, I'd say this is similar to a > > divide by zero execution. > > > I re-wrote the entire routine without the 8 or
Any insight greatly appreciated. From: "[email protected]"
That test changed my thinking to the 9,10 doesn't > > directly cause the problem, but rather that driving the signal is > > somehow messed up on the 10th cycle. NOW, I took a look over at Xilinx (god I hate their website) and I noticed in the download section: Update Type: BSDL Models Device Family: Spartan-3E File Type: ZIP (384 For a while I never got any message, but now I'm > > getting the > > > warning:impact:2217 error shows in the status register, CRC Error Bit > > is I change the VHDL code, and I change the results.
I don't know how to use the place and > > route simulation, or whether or not modelsim will show the error. > > nothing that ANY simulation could ever show I have had much success installing modern versions of ISE in Ubuntu and Fedora. Use the latest version of the software available from the > > > Download Center > > > > Configuration via PROM: > > > > B1. File
Antti PS next Antti-Brain will have section for ISE 11.1 and 6/6 FPGA's Article: 139998 Subject: Re: fpga locks up with slow signal, spartan chip, pin type issues. I recommend upgrading to WindowsXP or Linux. If not can you use LVDS for the interconnect? use USERCLOCK as startup clock it may make the CRC error to go away or not Antti Reply Posted by jleslie48 ●April 11, 2009On Apr 11, 9:20 am, "[email protected]"
Attempting to identify devices in the boundary-scan chain configuration...// *** BATCH CMD : Identify PROGRESS_START - Starting Operation. The obvious source is > >> DigiKey but they only have quantity one price. > >> Is there a better place to buy? > > > Which part do you want My question is: which manufacturer, family and/or device >> >> should I look for? from ISE From: "MM"
Ray Article: 139981 Subject: Re: ISE 10.1 installation troubles on windows Vista 32bit From: Bert_Paris
Regards, Gabor Article: 139987 Subject: Re: ISE 11.1 still no MP support :( From: General Schvantzkoph
The X-Server is different enough >> that the Xilinx GUI can't talk to it.) > >We use Ubuntu (& XP) and not SUSE, but your statement is surprising >since Xilinx officially look for the title: " fpga locks up with slow signal, spartan chip, pin type issues." Reply You might also like... Maybe the failure is due to increasing the clock frequency. Article: 139976 Subject: Re: fpga locks up with slow signal, spartan chip, pin type issues.